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Anna University M tech Computer Science Syllabus 2013
MA9110 OPERATIONSRESEARCH
UNIT I QUEUEING MODELS 9
Poisson Process –
Markovian Queues – Single and Multi-server Models – Little’s formula – Machine
Interference Model – Steady State analysis – Self Service Queue.
UNIT II ADVANCED QUEUEING MODELS 9
Non- Markovian Queues – Pollaczek Khintchine
Formula – Queues in Series – Open Queueing Networks –Closed Queueing networks.
UNIT III SIMULATION 9
Discrete Even Simulation – Monte – Carlo
Simulation – Stochastic Simulation – Applications to Queueing systems.
UNIT IV LINEAR PROGRAMMING 9
Formulation – Graphical solution – Simplex
method – Two phase method -Transportation and Assignment Problems.
Binary Search Trees – AVL Trees – Red-Black trees –
Multi-way Search Trees –B-Trees – Splay Trees – Tries.
UNIT IV MULTIMEDIA
STRUCTURES 9
Segment Trees – k-d Trees – Point Quad Trees
– MX-Quad Trees – R-Trees – TV-Trees.
UNIT V ALGORITHMS 9
Huffman Coding – Convex Hull – Topological Sort – Tree Vertex
Splitting – Activity Networks – Flow Shop Scheduling – Counting Binary Trees –
Introduction to Randomized Algorithms.
TOTAL = 45
REFERENCES
1.E.
Horowitz, S.Sahni and Dinesh Mehta, Fundamentals of Data structures in C++,
Uiversity Press, 2007.
2.E.
Horowitz, S. Sahni and S. Rajasekaran,
Computer Algorithms/C++, Second Edition, University Press, 2007.
3.G.
Brassard and P. Bratley, Algorithmics: Theory and Practice, Printice –Hall,
1988.
4.V.S.
Subramanian, Principles of Multimedia Database systems, Morgan Kaufman, 1998.
CP9113 ADVANCED COMPUTER ARCHITECTURE
L T P
C
3 0 0 3
UNIT I PIPELINING
AND ILP 9
Fundamentals of Computer Design - Measuring
and Reporting Performance - Instruction Level Parallelism and Its Exploitation
- Concepts and Challenges - Overcoming Data Hazards with Dynamic Scheduling –
Dynamic Branch Prediction - Speculation - Multiple Issue Processors – Case
Studies.
UNIT II
ADVANCED TECHNIQUES FOR
EXPLOITING ILP 9
Compiler
Techniques for Exposing ILP - Limitations on ILP for Realizable Processors -
Hardware versus Software Speculation - Multithreading: Using ILP Support to
Exploit Thread-level Parallelism - Performance and Efficiency in Advanced
Multiple Issue Processors - Case Studies.
UNIT III MULTIPROCESSORS 9
Symmetric and distributed shared memory
architectures – Cache coherence issues - Performance Issues – Synchronization
issues – Models of Memory Consistency - Interconnection networks – Buses,
crossbar and multi-stage switches.
UNIT IV MULTI-CORE
ARCHITECTURES 9
Software and hardware multithreading – SMT and CMP
architectures – Design issues – Case studies – Intel Multi-core architecture –
SUN CMP architecture – IBM cell architecture.- hp architecture.
UNIT V MEMORY
HIERARCHY DESIGN9
Introduction - Optimizations of Cache Performance -
Memory Technology and Optimizations - Protection: Virtual Memory and Virtual
Machines - Design of Memory Hierarchies - Case Studies.
TOTAL - 45
REFERENCES
1.John L. Hennessey and David A. Patterson, “
Computer Architecture – A quantitative approach”, Morgan Kaufmann / Elsevier, 4th. edition, 2007.
2.David E. Culler, Jaswinder Pal Singh, “Parallel
Computing Architecture : A hardware/ software approach” , Morgan Kaufmann / Elsevier, 1997.
3.William
Stallings, “ Computer Organization and Architecture – Designing for
Performance”, Pearson Education, Seventh Edition, 2006.
CP9114
OBJECT ORIENTED SYSTEMS ENGINEERING
L T P C
3 0 0 3
UNIT I CLASSICAL PARADIGM
System Concepts – Project Organization –
Communication – Project Management
UNIT II
PROCESS MODELS
Life cycle models – Unified Process –
Iterative and Incremental – Workflow – Agile Processes
Stephen
Schach, Software Engineering 7th
ed, McGraw-Hill, 2007.
Ivar
Jacobson, Grady Booch, James Rumbaugh, The Unified Software Development
Process, Pearson Education, 1999.
Alistair
Cockburn, Agile Software Development 2nd ed, Pearson Education,
2007.
CP9115 NETWORK ENGINEERING
AND MANAGEMENT
L T P C
3 0 0 3
UNIT I FOUNDATIONS OF
NETWORKING 9
Communication Networks – Network Elements –
Switched Networks and Shared media Networks – Probabilistic Model and
Deterministic Model – Datagrams and Virtual Circuits – Multiplexing – Switching
- Error and Flow Control – Congestion
Control – Layered Architecture – Network Externalities – Service Integration –
Modern Applications
UNIT II QUALITY OF SERVICE 9
Traffic Characteristics and Descriptors – Quality of Service and Metrics
– Best Effort model and Guaranteed Service Model – Limitations of IP networks –
Scheduling and Dropping policies for BE and GS models – Traffic Shaping
algorithms – End to End solutions – Laissez Faire Approach – Possible
improvements in TCP – Significance of UDP in inelastic traffic
UNIT III HIGH PERFORMANCE NETWORKS 9
Integrated Services Architecture – Components
and Services – Differentiated Services Networks – Per Hop Behaviour – Admission
Control – MPLS Networks – Principles and Mechanisms – Label Stacking – RSVP –
RTP/RTCP
UNIT IV HIGH SPEED NETWORKS 9
Optical links – WDM systems – Optical Cross
Connects – Optical paths and Networks – Principles of ATM Networks – B-ISDN/ATM
Reference Model – ATM Header Structure – ATM Adaptation Layer – Management and
Control – Service Categories and Traffic descriptors in ATM networks
UNIT V NETWORK MANAGEMENT 9
ICMP the Forerunner – Monitoring and Control
– Network Management Systems – Abstract Syntax Notation – CMIP – SNMP
Communication Model – SNMP MIB Group – Functional Model – Major changes in
SNMPv2 and SNMPv3 – Remote monitoring – RMON SMI and MIB
Larry
L Peterson and Bruce S Davie, ‘Computer Networks: A Systems Approach’,
Fourth Edition, Morgan Kaufman Publishers, 2007.
Jean
Warland and Pravin Vareya, ‘High Performance Networks’, Morgan Kauffman Publishers, 2002
William
Stallings, ‘High Speed Networks: Performance and Quality of Service’, 2nd
Edition, Pearson Education, 2002.
Mani
Subramaniam, ‘Network Management: Principles and Practices’, Pearson
Education, 2000
Kasera
and Seth, ‘ATM Networks: Concepts and Protocols’, Tata McGraw Hill, 2002.
CP9118
DATA
STRUCTURES LABORATORY
L T P C
0 0 3 2
Implementation
of multi-dimensional structures such as matrices, triangular matrices,
diagonal matrices, etc into a one dimensional array (atleast any two)
Implementation
of any two of the following Heap structures